This invention concerns a fabrication technique for a semiconductor integrated circuit device, and, it particularly relates to a technique effective for application to the dry etching technique for a wiring layer connected to a ferroelectric film or a highly dielectric film by way of an electrode layer.
Electron cyclotron resonance (ECR) plasma etching is one of dry etching techniques. This system has advantages in that high density plasmas (from 1011 to 1012 cmxe2x88x923)is provided and high speed etching can be carried out, the mean free process of ions is increased due to low voltage operation to align the directions of ions and obtain anisotropic shapes easily, accurate shape control is performed since ion energy can be controlled independently of plasma formation, metal contamination does not occur because of absence of the upper electrode, and that occurrence of obstacles is reduced in conjunction with the low voltage operation.
Accordingly, the ECR plasma etching has been introduced in the dry etching techniques for semiconductor integrated circuit devices that require fine fabrication and less dusting and adopted in various etching processes.
The ECR plasma etching apparatus described above are described, for example, in xe2x80x9cFoundation for Superfine Fabricationxe2x80x9d, written by Tatsuo Asanae, p 74, FIG. 4.10(b), published from Nikkan Kogyo Shinbunsha, on Mar. 25, 1993.
However, for applying the ECR plasma etching to the fabrication steps of a wiring layer in FeRAM (Ferroelectric Random Access Memory), the present inventors have found the following problems.
That is, when a wiring layer, for example, a titanium nitride (TiN) film or an aluminum (Al) alloy film connected to a PZT (PbZrTiO3) film by way of an electrode layer, for example, a platinum (Pt) film is fabricated by ECR plasma etching using a photoresist pattern as a mask and, successively, an asher treatment for removing the photoresist pattern is applied to a semiconductor wafer (generally, the dry etching treatment and the ashing treatment are conducted by one identical multi-chamber type apparatus by transferring a wafer to be fabricated from a dry etching treatment chamber to an ashing treatment chamber with no exposure to atmospheric air), apparent degradation was observed in the result of an acceleration test for the PZT characteristics, for example, amount of polarization QSW (length of C-axis segment of a hysteresis characteristic curve for a ferroelectric capacitor on a CV plane, which corresponds, in principle, to amount of charges accumulated in a storage cell) (depolarization) . That is, after patterning a TiN wiring, when accelerated degradation test was applied at 150xc2x0 C. for 100 hrs, it was found that the characteristics were degraded to less than the lower limit of 5 xcexcC/cm2 for the amount of polarization required for the products in about 10 hrs, as to those fabricated by ECR plasma etching and applied with an ashing treatment in a low temperature region at a temperature on the back of wafer of about 50xc2x0 C. to 60xc2x0 C. (from 100 to 110xc2x0 C. as the temperature on the upper surface of the wafer).
On the contrary, it has been found that those etched by inducely coupled plasma etching or those etched by ECR plasma etching and then subjected to the ashing treatment in a high temperature region, for example, at a temperature on the back of the wafer of 240xc2x0 C., retained the amount of polarization more than the lower limit described above even after the accelerated test for 100 hrs (corresponding to continuous use for about 10 years).
Referring more specifically, those etched by the inducely coupled plasma etching and then subjected to the ashing treatment in a high temperature region, for example, at 240xc2x0 C. for the temperature on the back of a wafer showed further preferred characteristics in the accelerated degradation test, and relatively preferred characteristics were shown by the plasma density in the inducely coupled plasma etching in the lower density area (from 1.0xc3x971010 to 1.0xc3x971011/cm3). Further, it was found for the ashing gas that a preferred characteristic was shown by adding steams compared with a gas mainly comprising oxygen (or solely consisting of oxygen) and, further, a more preferred characteristic was shown by adding a fluorocarbon gas such as CF4. Referring to the ashing temperature, in a case of PZT having a curie point Tc of about 450xc2x0 C., the effect begins to develop at the temperature on the upper surface of the wafer of 150xc2x0 C. (⅓ for Tc on the Celsius indication here and hereafter) or higher, it become rather remarkable at 200xc2x0 C. (about 40% for Tc) or higher and a further remarkable effect is obtained at 300xc2x0 C. (⅔ of Tc) or higher. In the system heating at the back of the wafer described above, in view of the temperature set to the wafer, that is, the temperature on the back of the wafer, it is a value obtained by subtracting about 50xc2x0 C. from the temperature on each upper surface of the wafer.
The ashing temperature may be further nearer to the curie point or higher in view of the temperature on the upper surface of the wafer. If there are no other problems, it may be considered theoretically that as the temperature is higher crystals restore more remarkably. Naturally, it should be lower than the melting point of inter-wiring materials (660xc2x0 C. in a case of aluminum).
It is considered that since ECR plasma etching has a plasma generation mechanism accompanied with strong magnetic fields, charge up damages or UV ray-induced damages are increased by poor uniformity of plasmas.
On the other hand, in a case of the inducely coupled plasma (hereinafter simply referred to as ICP), it is considered that the damages are decreased since relatively uniform plasmas are formed on the wafer. ICP is classified as a sort of plasma furnaces of accelerating electrons by induction coupling to conduct plasma excitation by applying an RF power (for example at 13.56 MHz) to coils or stripe-like or coiled antennas, and it does not accompany as a rule relatively strong magnetic fields for plasma excitation on the wafer to be treated in most cases (this also contributes to the uniformity of plasmas at the periphery of the wafer). It has a feature capable of attaining a uniform plasma distribution relatively simply by devising the shape and the arrangement of coils. Further, it is considered that recovery of perovskite crystals (PZT, BST, etc) proceeds more smoothly as the ashing temperature is higher.
While identical preferred damage characteristics may be obtained also by reactive ion etching such as capacitively coupled plasma (parallel plate type), reactive ion etching apparatus available at present involve a problem regarding other characteristics required for metal etching and they can not be applied at present, but leave a room for application if other characteristics are satisfied.
Further, for DRAM, when a perovskite type highly dielectric material such as BST is intended to be formed into a capacitor insulative film, it is considered that identical preferred damage characteristics can be obtained by etching by the inducely coupled plasma and an ashing treatment at a relatively high temperature. That is, the dielectric constant of the capacitor insulative film shows no abrupt degradation (lowering of the dielectric constant in this case) even by the same accelerated test. In this ashing, what corresponds to the curie point Tc described previously is a crystallizing annealing temperature Tcr conducted after forming the capacitor insulative film by CVD or the like (heat treatment temperature for converting from amorphous to crystalline film), which is at 700xc2x0 C. to 800xc2x0 C. in a case of BST. Accordingly, the effect begins to develop at about 250xc2x0 C. for the temperature on the upper surface of the wafer (200xc2x0 C. for the temperature on the lower surface of a wafer), the effect becomes rather conspicuous at 330xc2x0 C. (280xc2x0 C. for the temperature on the lower surface of the wafer) or higher and the effect becomes more remarkable at 500xc2x0 C. (450xc2x0 C. for the temperature on the lower surface of the wafer) or higher.
An object of this invention is to provide an etching technique for a wiring layer capable of decreasing the degradation characteristics in a ferroelectric film in FeRAM.
Other objects and novel features of this invention will become apparent by referring to the descriptions of this specification and appended drawings.
Among the inventions disclosed in this application, outline for typical ones will be explained simply as below.
(1) In a method for fabricating a semiconductor integrated circuit device according to this invention, when a wiring layer to be connected to a ferroelectric film having a perovskite structure by way of an electrode layer, a wiring material deposited on a semiconductor substrate is at first fabricated by dry etching using inducely coupled plasma and then an asher treatment is conducted by using inducely coupled plasma of introducing a gas mixture of O2+CF4+H2O at a temperature in the upper surface of a semiconductor substrate, for example, of 300xc2x0 C. or higher.
(2) In a method for fabricating a semiconductor integrated circuit device according to this invention, the plasma density of the inducely coupled plasma is 1.0xc3x971010 to 1.0xc3x971011 cmxe2x88x923 in the method of fabricating the semiconductor integrated circuit device as defined in (1) above. It is of course possible also in a higher density region.
(3) In a method for fabricating a semiconductor integrated circuit device according to this invention, the wiring material comprises a titanium nitride film or an aluminum alloy film in the method for fabricating the semiconductor integrated circuit device as defined in (1) above.
(4) In a method for fabricating a semiconductor integrated circuit device according to this invention, the ferroelectric film comprises a PbZrTiO3 film or a PbLaZrTiO3 (simply referred to as PlZt) film in the method for fabricating the semiconductor integrated circuit device as defined in (1) above.
In the means described above, since dry etching by low density plasmas using the inducely coupled plasma is adopted when the wiring layer connected to the ferroelectric film by way of the electrode layer is formed and plasmas of good uniformity can be obtained, uniformity of charges flying to the semiconductor wafer is improved and, further, charge up damages are decreased do to the absence of magnetic fields on the semiconductor wafer.
Further, the ahser treatment using the inducely coupled plasma is conducted by setting the temperature on the upper surface of the semiconductor wafer to, for example, 300xc2x0 C. or higher and introducing the gas mixture of O2+CF4 +H2O, crystals of the ferroelectric film are re-arranged and damages of the ferroelectric film caused by dry etching using the inducely coupled plasma can be recovered.
Other outlines of the invention according to the present application will be simply summarized as below for each of the items.
(1). A method for fabricating a semiconductor integrated circuit device for forming a wiring layer to be connected to a dielectric film by way of an electrode layer, wherein a wiring material deposited on a semiconductor substrate is fabricated by dry etching using inducely coupled plasma and then an asher treatment is conducted using inducely coupled plasma of introducing a gas mixture to which an H2O gas is added at a temperature on the upper surface of the semiconductor substrate, for example of 300xc2x0 C. or higher.
(2). A method for fabricating a semiconductor integrated circuit device as defined in (1) above, wherein the gas mixture is a gas mixture comprising O2+CF4+H2O.
(3). A method for fabricating a semiconductor integrated circuit device as defined in (1) above, wherein a plasma density in the inducely coupled plasmas is from 1.0xc3x971010 to 1.0xc3x971011 cmxe2x88x923.
(4). A method for fabricating a semiconductor integrated circuit device as defined in (1) above, wherein the wiring layer is formed as a partial wiring and a wiring layer to be connected with the partial wiring is included.
(5). A method for fabricating a semiconductor integrated circuit device as defined in (1) above, wherein the wiring material comprises a titanium nitride film or an aluminum alloy film.
(6). A method for fabricating a semiconductor integrated circuit device as defined in (1) above, wherein the dielectric film comprises a ferroelectric film or a highly dielectric film having a perovskite structure.
(7). A method for fabricating a semiconductor integrated circuit device as defined in (6) above, wherein the ferroelectric material comprises a PbZrTiO3 film or a PbLaZrTiO3 film, and the highly dielectric film comprises a BaSrTiO3 (simply referred to as BST) film.